It has been found that the wafer level package (WLP) is currently the least expensive package of all. The reason for this is that the chips are contacted directly on a PCB (Printed Circuit Board) and the wire bonding, the critical leadframe and the encapsulation are no longer needed. The wafer level package has extremely small dimensions combined with extremely good electrical properties. In addition, all possibilities for testing and reworking are retained, and customary pick-and-place machines for printed circuit boards can be used.
“Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies). These singulated chips are then mounted directly on a substrate.
Furthermore, chips require an enclosure of a synthetic material, for example a polymer. This enclosure has the task of protecting the chip from corrosive environmental influences, in particular at the sawn edge in the region of the sequence of layers, and also, on a micromechanical level, protecting the fine bonding wires from damage and, on a macromechanical level, protecting the hard but brittle silicon from rupture.
This protection is brought about in the case of most chips or packages by enclosure in a synthetic material, known as a mold cap. For this purpose, the package together with the leadframe or some other carrier element, is completely encapsulated in a thermocuring epoxy resin (molding compound) in a mold. In this operation, the sawn edges, the bonding wires and the silicon are protected and, at the same time, the leadframe or the carrier element is incorporated.
In the case of the less expensive WLP, the task of protecting the bonding wires and the incorporation of the leadframe are no longer needed. In the case of the WLP, all that is necessary is to protect the sawn edges in the region of the layers from corrosive environmental influences and to protect the brittle silicon from the back side. To achieve this, the chips are singulated from the wafer assembly and respectively mounted on a board, for example in a way corresponding to flip-chip technology, and the back side of the chip and the sawn edges of the chip are subsequently encapsulated in a thermocuring epoxy resin.
However, the WLP has the disadvantage that it can only be used for small chips with an edge length of up to at most 2.5 mm. The reason for this is that larger chips have longer displacements under expansion (great DNP), which, in combination with the very different coefficients of expansion of 2.3 ppm/K in the case of the chip and 20 ppm/K in the case of the printed circuit board (PCB, glass-fiber reinforced epoxy resin), bring about a gradual detachment of the external soldered connections under the unavoidable temperature changes taking place. This means that the chips may fail prematurely in the thermal cycling test on the board (PCB), in that soldered connections develop cracks.
To circumvent this problem, two basic possibilities have so far become known.
The first possibility is to bring about a kind of “constrained securement” of the chip and printed circuit board. This can be achieved for example by an “underfill” between the chip and the printed circuit board, or a “polymer collar,” which partly encloses the solder balls on the chip.
However, the “constrained securement” in the case of the “underfill,” that is the introduction of a molding material between the chip and the printed circuit board by using capillary action, has the disadvantage that a repair (reworking) is only possible with difficulty. In addition, the “underfill” requires an additional working step. Furthermore, in the case of very large chips, such as DRAMs, the “underfill” is not adequately reliable in the long term.
The use of a “collar” has only a limited effect and is not adequate in the case of large chips, such as DRAMs.
The second possibility is that of a “free securement” of the chip and the printed circuit board. This can be achieved for example by “microsprings” (connecting elements designed in the manner of springs), “soft bumps” (elastic or compliant contact bumps), the use of a chip mounting film (tape), or a “double ball redistribution” (wiring interposer with in each case two contact balls one above the other, the lower contact ball being embedded in epoxy resin).
However, it can be stated that all the “free securements” have a major disadvantage in common. If the distance (H) between the chip and the printed circuit board is small (the shearing force at the solder ball is proportional to DNP divided by H), the “gain in freedom,” and consequently the “gain in reliability,” is also small. If the distance (H) between the chip and the printed circuit board is great, the “gain in freedom,” and consequently the “gain in reliability,” is indeed great, but at the same time the construction becomes thicker, which is at odds with increasing miniaturization.
This relationship can be expressed by a general formula:γ=ΔT(CTEdie−CTEboard)DNP/H where                y=shearing force        CTE=coefficient of thermal expansion of the die or of the board        ΔT=temperature range of the stress cycle        DNP=distance to the neutral point of the soldered connections        H=distance between die (chip) and board        
It is evident from this formula that the shearing force depends in particular on H and decreases with increasing H.
U.S. Pat. No. 5,851,845 discloses a method for the packaging of a semiconductor chip. This method is based on the problem that, in the chip-on-board mounting of an unpackaged chip on a printed circuit board, a thermally induced stress occurs. This thermal stress is produced by the mismatch between the coefficients of thermal expansion (CTE) of the chip and the printed circuit board.
The method therefore provides that a thinned chip in the wafer assembly is mounted on a substrate with a compliant adhesive layer interposed. The compliant adhesive layer has the task of absorbing thermally induced stress. Silicon, ceramic or else glass-fiber reinforced epoxy resin (e.g. FR-4) may be used as the substrate material. Polyimide, epoxy resin, silicone or the like come into consideration for example for the compliant adhesive layer. After singulation, the correspondingly equipped chip can then be mounted on printed circuit boards.
Finally, U.S. Pat. Publication No. 2002/197771 A1 discloses a method for thinning a wafer by means of CMP (chemical mechanical polishing) and also an arrangement for protecting the thinned chips. To protect the chip from damage or rupture, a reinforcing means is applied to its back side. A flat sheet or a polyimide or polysilicone coating is used here as the reinforcing means. The invention is therefore based on the object of presenting a wafer level package which eliminates the disadvantages of the prior art. Problems of thermal mismatch and of board level reliability are eliminated, the accomplishment of adequately thin structures is allowed and dependable protection of the chip edges is allowed. Furthermore, methods by which such a wafer level package can be accomplished are to be presented.
This is achieved by the chip being thinned extremely from the back side and bonded onto a fiber reinforced synthetic resin sheet, forming a solidly bonded assembly that cannot come apart in the customary temperature range, and the edges of the assembly being at least partly coated with a polymer.
The synthetic resin sheet may in this case be mounted on the back side or the front side of the chip.
In continuation of the invention, the synthetic resin sheet on the front side of the chip is provided with via holes at the same pitch as the solder balls which are mounted on the side of the synthetic resin sheet that is opposite from the chip, the chip being mounted “face-down” on the synthetic resin sheet and electrically connected by the via holes.
The thickness of the thinned chips is around 10 μm to 100 μm and the thickness of the synthetic resin sheet is around 100–2000 μm.
The chips are preferably equipped with an M3-RDL system and with solder balls in a square 0.5 mm pitch.